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• VHDL Free Model Foundation
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• Automatic Extraction of the Control Flow Machine and Application to Evaluating Coverage of Verification Vectors - UT Austin
  Hoskote suggests that most design errors deal with the control flow in the circuit. This paper presents a tecjnique for automatically extracting the Control Flow Machine of a design from its circuit description at any level. The extraction is done on the basic of the underlying mathematical model and is independent of the description style. This Extracted Control Flow Machine (ECFM) has a much smaller state space but exhibits the same flow as the origional circuit. Hoskote then proposes a pragmatic and meaningful definition of functional coverage as the amount of control behavior covered and illustrates how the ECFM can be used for estimation of the coverage achieved by a set of verification vectors. This information can then be used to improve the quality of tests.
• A Unified Framework for Design Validation and Manufacturing Test - UT Austin
  Moundanos presents how abstraction techniques can assist conventional ATPG tools when attacking hard to detect faults. The same abstraction can also be used in design verification to increase the level of confidence in a design following simulation, by providing a meaningful measure of the coverage achieved by the verification vectors.

Related Topics

• Microprocessor Verification
• Formal Microprocessor Verification
• Formal Hardware Verification
• Knowledge-Based Testing
• IC Interconnect Products - ackaging, Printed Circuits and Assembly Services